This invention is in the field of solid-state memory. Embodiments of this invention are more specifically directed to static random access memory (SRAM) cells and devices.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled the shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM but also in SRAM realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
An example of a conventional SRAM cell is shown in FIG. 1a. In this example, SRAM cell 2 is a conventional six-transistor (6-T) static memory cell 2, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 2 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass-gate transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass-gate transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass-gate transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 2 for a read operation, word line WLj is then energized, turning on pass-gate transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
As mentioned above, device variability can cause read and write failures, particularly in memory cells constructed with sub-micron minimum feature size transistors. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, in an attempt to write a low logic level to storage node SNT of cell 2 of FIG. 1a, if bit line BLTk is unable to sufficiently discharge storage node SNT to the trip the inverters, cell 2 may not latch to the desired data state.
Cell stability failures are the converse of write failures—a write failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily, such as may occur to a memory cell in a selected row but an unselected column (i.e., a “half-selected” cell) during a write to a cell in a selected column in its same row. Noise of sufficient magnitude coupling to the bit lines of the half-selected columns, during a write to the selected columns in the same row, can cause a false write of data to those half-selected columns. In effect, such write cycle noise can be of sufficient magnitude as to trip the inverters of one or more of the half-selected cells. The possibility of such stability failure is exacerbated by device mismatch and variability, as discussed above.
In conventional SRAM cells such as 6-T SRAM cell 2 of FIG. 1a, the designer is therefore faced with a tradeoff between cell stability on one hand, and write margin on the other. In a general sense, cell stability is favored by pass-gate transistors 5a, 5b having relatively weak drive as compared with load transistors 3 and driver transistors 4, because this results in weak coupling between the bit lines and storage nodes and relatively strong drive of the latched state at storage nodes SNT, SNB. Conversely, write margin is favored by pass-gate transistors 5a, 5b having relatively strong drive as compared with load transistors 3 and driver transistors 4, because this enables strong coupling between the bit lines and storage nodes, resulting in storage nodes SNT, SNB having weak resistance to changing state. Accordingly, the design of conventional 6-T SRAM cells 2 involves a tradeoff between these two vulnerabilities.
Unfortunately, the design window in which both adequate cell stability and adequate write margin can be attained is becoming smaller with continued scaling-down of device feature sizes, for the reasons mentioned above. In addition, it has been observed that the relative drive capability of p-channel MOS transistors relative to re-channel MOS transistors is increasing as device feature sizes continue to shrink, which skews the design window toward cell stability over write margin.
One conventional approach toward relaxing these ever-tightening design constraints is known in the art as “write-assist”. According to this approach, the power supply bias applied to SRAM cells (e.g., power supply voltage Vdda of FIG. 1a) in write cycles is reduced, or disconnected so as to float. Conventional write-assist circuitry includes a power switch associated with each column of an array, or in some cases associated with multiple columns. Floating write assist bias in write cycles is attained by the power switch disconnecting cells in the selected column from the power supply voltage. In one approach, reduced voltage write assist bias turns off, in write cycles, a power switch that is connected in parallel with a diode-connected transistor between the memory cells and the power supply voltage. The cell bias in the selected column is thus at least a diode voltage drop from the full power supply voltage, during write cycles. For either reduced or floating write assist bias, the drive of the load and driver transistors in the SRAM cell is reduced relative to the drive of the pass-gate transistors, making it easier for the low level bit line to flip the state of the addressed cell.
Another conventional approach addressing the shrinking design window to satisfy both cell stability and write margin constraints is the construction of high performance SRAM memories using eight transistor (“8-T”) memory cells. As known in the art, the 8-T SRAM cell consists of a 6-T latch as shown in FIG. 1a, in combination with a two-transistor read buffer. Each cell receives separate read and write word lines and separate read and write bit lines. The complementary write bit lines are selectively coupled to the storage nodes of the 6-T latch by the pass-gate transistors gated by the write word line, as in the conventional 6-T SRAM cell. The read buffer includes the series connection of a drive transistor gated by one of the storage nodes and a pass-gate transistor gated by the read word line, connected between a reference voltage (e.g., ground) and the read bit line. In this 8-T construction, the pass-gate transistors involved in the write cycle can have strong drive to provide good write margin, without affecting cell stability during read operations (because those pass-gate transistors remain off). However, in an interleaved architecture, half-selected cells in a write cycle (i.e., cells in the selected row that are not being written) can still exhibit cell instability, because the write word line will be energized in that situation. To avoid this situation, the 8-T cells are implemented in a non-interleaved architecture, in which the entire selected row of cells is written in a write cycle. As known in the art, non-interleaved memory arrays are vulnerable to multiple-bit soft error failures, and consume additional chip area. In addition, these conventional 8-T cells source a single-ended read, rather than the differential signal sourced by the 6-T cell; either the read signal is reduced as a result, or the device sizes for the read buffer must be increased to compensate for that weaker signal.
In many conventional implementations, the transistors in the 6-T SRAM cell are constructed to symmetrically match one another as closely as possible, in attempts to optimize stability between the two data states. However, it is also known in the art that cell stability in some SRAM 6-T cells can be improved by intentional asymmetry in the construction of the SRAM cell. FIG. 1b illustrates examples of the well-known DC “butterfly” transfer function curves for a 6-T SRAM cell such as cell 2 of FIG. 1a, to illustrate the potential benefit of asymmetric construction.
In the familiar fashion, the butterfly curves of FIG. 1b illustrate the voltages at storage nodes SNT, SNB of cell 2 in their two potential data states, and transitions between the two. In this example, the “1” data state is at stable point DS1 at which voltage VSNT at storage node SNT is near power supply voltage Vdda and voltage VSNB at storage node SNB is near ground (Vssa); conversely, the “0” data state is at stable point DS0, with voltage VSNB near power supply voltage Vdda and voltage VSNT near ground. Transfer characteristic TF1-0 shows the voltages at storage nodes SNT, SNB for a transition from stable point DS1 to stable point DS0 (a “1” to “0” transition). For cell 2 of symmetric construction, in which n-channel driver transistors 4a, 4b are matched to one another, and p-channel load transistors 3a, 3b are matched to one another, transfer characteristic TF0-1 shows the voltages at storage nodes SNT, SNB for the transition from stable point DS0 to stable point DS1 (a “0” to “1” transition).
As mentioned above, cell stability refers to the ability of SRAM cell 2 to withstand static noise without changing states. A quantitative measure of cell stability is referred to in the art as static noise margin, which corresponds to the noise at a storage node that the cell can tolerate without changing its logic state, and can be approximated by the area of the largest square that fits between transfer characteristics for the two state transitions. For example, FIG. 1b illustrates static noise margin SNMSYM for SRAM cell 2 of symmetric construction case, as the area of the largest square that fits between transfer characteristics TF1-0, TF0-1.
As mentioned above, asymmetric construction of SRAM cell 2 can, in some situations, increase the cell stability (i.e., increase the static noise margin). FIG. 1b illustrates such increased static noise margin, for an example of an SRAM cell 2 in which driver transistor 4a has a higher threshold voltage (e.g., 100 mV) than that of driver transistor 4b. Transfer characteristic TF0-1′ illustrates the effect of this asymmetric construction on the “0” to “1” transition, and the resulting static noise margin SNMASYM. As shown by the example of FIG. 1b, in that particular situation, static noise margin SNMASYM is improved for the asymmetric construction of SRAM cell 2 over that shown by static noise margin SNMSYM for its symmetric construction.
Recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. It has been discovered that the tuning of strain in the crystal lattice of metal-oxide-semiconductor (MOS) transistor channel regions can enhance carrier mobility in those regions. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of an MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. In a general sense, longitudinal compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and longitudinal tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor.
One conventional strain engineering approach is referred to in the art as “dual stress liner”, or “DSL”, technology. According to this approach, a silicon nitride layer of either tensile or compressive characteristics is deposited over the surface of the integrated circuit, and patterned and etched to remain only over the active regions (i.e., source and drain regions) of transistors that are to receive the resulting stress. Tensile silicon nitride is used to enhance n-channel MOS transistors, and compressive silicon nitride is used to enhance p-channel MOS transistors. In CMOS integrated circuits including both p-channel and n-channel MOS transistors, both tensile and compressive nitride layers can be applied, to the n-channel and p-channel transistors respectively, to improve the performance characteristics of both conductivity types.